Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache.
Zhi-Yong LiuHsiu-Chuan ShihBing-Yang LinCheng-Wen WuPublished in: IEEE Des. Test (2017)
Keyphrases
- low power
- low latency
- high speed
- cmos technology
- vlsi architecture
- real time
- power consumption
- low cost
- main memory
- memory subsystem
- low voltage
- embedded dram
- mixed signal
- dynamic random access memory
- digital signal processing
- highly efficient
- nm technology
- single chip
- low power consumption
- high throughput
- logic circuits
- high density
- data center
- data structure
- memory access
- index structure
- multithreading
- virtual machine
- power dissipation
- stream processing
- data flow
- data acquisition
- query processing