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Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs.
Shin-Shiun Chen
Chun-Kai Hsu
Hsiu-Chuan Shih
Jen-Chieh Yeh
Cheng-Wen Wu
Published in:
ASP-DAC (2013)
Keyphrases
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memory subsystem
power consumption
ibm power processor
main memory
high density
real time
high speed
data integration
parallel processing
combining multiple
instruction set
ibm zenterprise
dynamic random access memory
database management systems
multiprocessor systems