An Enhanced EDAC Methodology for Low Power PSRAM.

Po-Yuan Chen Yi-Ting Yeh Chao-Hsun Chen Jen-Chieh Yeh Cheng-Wen Wu Jeng-Shen Lee Yu-Chang Lin

Published in: ITC (2006)

Keyphrases

low power
power consumption
high speed
low cost
single chip
high power
wireless transmission
vlsi circuits
digital signal processing
vlsi architecture
logic circuits
power dissipation
gate array
image sensor
power reduction
design methodology
signal processor
ultra low power
hardware and software
low complexity