Ching-Te Chiu

ORCID

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 51

Top Venues

ICASSP

ISCAS

J. Signal Process. Syst.

SiPS

University of Maryland, College Park, MD, USA (PHD)

Education History

University of Maryland, College Park, MD, USA

PHD

Publications

Yi-Fan Chen, Yu-Jen Chang, Ching-Te Chiu, Ming-Long Huang, Geng-Ming Liang, Chao-Lin Lee, Jenq-Kuen Lee, Ping-Yu Hsieh, Wei-Chih Lai
Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction. ISCAS (2024)
An-Ting Hsieh, Ching-Te Chiu, Tsai-Chieh Chen, Mao-Hsiu Hsu, Wenyong Long
Feature Points based Residual UNet with Nonlinear Decay Rate for Partial Wet Fingerprint Restoration and Recognition. ISCAS (2024)
Yu-Min Chiu, Ching-Te Chiu, Dao-Heng Luo
Multi-Layer Relation Knowledge Distillation For Fingerprint Restoration. ICASSP (2024)
Shi-Zong Huang, Ching-Te Chiu, Yu-Jen Chang
Machine Learning Based Action Recognition with Modular CNN. APSIPA ASC (2023)
Wei-Jyun Chen, Ching-Te Chiu, Ting-Chun Lin
Landmark-Based Adversarial Network for RGB-D Pose Invariant Face Recognition. AICAS (2023)
Wei-Chen Lin, Ching-Te Chiu, Kuan-Chang Shih
RGB-D Based Pose-Invariant Face Recognition Via Attention Decomposition Module. ICASSP (2023)
Ching-Chen Wang, Ching-Te Chiu, Jheng-Yi Chang
EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search. J. Signal Process. Syst. 95 (5) (2023)
Chih-Han Cheng, Ching-Te Chiu, Chia-Yu Kuan, Yu-Chi Su, Kuan-Hsien Liu, Tsung-Chan Lee, Jia-Lin Chen, Jie-Yu Luo, Wei-Chang Chung, Yao-Ren Chang, Kuan-Ying Ho
Multiple Training Stage Image Enhancement Enrolled With CCRGAN Pseudo Templates for Large Area Dry Fingerprint Recognition. IEEE Access 11 (2023)
Shu-Yun Wu, Ching-Te Chiu, Yung-Ching Hsu
Pose Aware RGBD-based Face Recognition System With Hierarchical Bilinear Pooling. NEWCAS (2023)
Hsueh-Kai Kuo, Ching-Te Chiu, Lien-Chieh Huang
Low Temperature and Dry Fingerprint Restoration with Ridge Loss and Orientation. NEWCAS (2023)
Yu-Ting Li, Ching-Te Chiu, An-Ting Hsieh, Mao-Hsiu Hsu, Wenyong Long, Jui-Min Hsu
PGT-Net: Progressive Guided Multi-task Neural Network for Small-area Wet Fingerprint Denoising and Recognition. CoRR (2023)
Yu-Chi Su, Ching-Te Chiu, Chih-Han Cheng, Kuan-Hsien Liu, Tsung-Chan Lee, Jia-Lin Chen, Jie-Yu Luo, Wei-Chang Chung, Yao-Ren Chang, Kuan-Ying Ho
CPGAN: Collective Punishment Generative Adversarial Network for Dry Fingerprint Image Enhancement. AICAS (2023)
Yen-Yu Cheng, Ching-Te Chiu, Yi-Fan Chen
RGBD-based Hardware Friendly Head Pose Estimation System via Convolutional attention module. ISCAS (2022)
Jheng-Yi Chang, Ching-Te Chiu, Pin-Hsuan Chen
Lightweight and Efficient Neural Network Using Progressively Greedy Search. AICAS (2022)
Ching-Te Chiu, Yu-Chun Ding, Wei-Chen Lin, Wei-Jyun Chen, Shu-Yun Wu, Chao-Tsung Huang, Chun-Yeh Lin, Chia-Yu Chang, Meng-Jui Lee, Shimazu Tatsunori, Tsung Chen, Fan-Yi Lin, Yuan-Hao Huang
Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Jie-Yu Luo, Ching-Te Chiu, An-Ting Hsieh
Multi-View RGB-D Based 3D Point Cloud Face Model Reconstruction System. ISCAS (2022)
Ching-Chen Wang, Yu-Chun Ding, Ching-Te Chiu, Chao-Tsung Huang, Yen-Yu Cheng, Shih-Yi Sun, Chih-Han Cheng, Hsueh-Kai Kuo
Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (10) (2021)
Yen-Yu Pu, Ching-Te Chiu, Shu-Yun Wu
Real-Time Edge Attention-Based Learning for Low-Light One-Stage Object Detection. APSIPA ASC (2021)
Ching-Tung Tang, Ching-Te Chiu, Wei-Jyun Chen
3D Landmark-based Face Detection and Recognition System for Large Poses. APSIPA ASC (2021)
Shan-Chien Hsiao, Ching-Te Chiu
Efficient 2D Keypoint-based Hand Pose Estimation. CSCI (2021)
Jiou-Ai Lin, Ching-Te Chiu, Yen-Yu Cheng
Object Detection in RGB-D Images via Anchor Box with Multi-Reduced Region Proposal Network and Multi-Pooling. J. Signal Process. Syst. 93 (10) (2021)
Kuan-Ting Lin, Ching-Te Chiu, Jheng-Yi Chang, Shan-Chien Hsiao
High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator. ISCAS (2021)
Tzu-Ying Lin, Ching-Te Chiu, Ching-Tung Tang
Rgb-D Based Multi-Modal Deep Learning for Face Identification. ICASSP (2020)
Chia-Ho Hsu, Ching-Te Chiu, Chia-Yu Kuan
Fast Single-View 3D Object Reconstruction with Fine Details Through Dilated Downsample and Multi-Path Upsample Deep Neural Network. ICASSP (2020)
Kuan-Hung Shih, Ching-Te Chiu, Jiou-Ai Lin, Yen-Yu Bu
Real-Time Object Detection With Reduced Region Proposal Network via Multi-Feature Concatenation. IEEE Trans. Neural Networks Learn. Syst. 31 (6) (2020)
Yung-Chang Chang, Cihun-Siyong Alex Gong, Ching-Te Chiu
Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy. J. Signal Process. Syst. 92 (4) (2020)
Meng-Chieh Wu, Ching-Te Chiu
Multi-teacher knowledge distillation for compressed video action recognition based on deep learning. J. Syst. Archit. 103 (2020)
Kuang-Chien Li, Ching-Te Chiu, Shan-Chien Hsiao
Semantic Segmentation via Enhancing Context Information by Fusing Multiple High-Level Features. SiPS (2020)
Wen-Yi Lo, Ching-Te Chiu, Jie-Yu Luo
Depth Estimation From Single Image Through Multi-Path-Multi-Rate Diverse Feature Extractor. ICASSP (2020)
Jiou-Ai Lin, Ching-Te Chiu, Yen-Yu Cheng
Object Detection with Color and Depth Images with Multi-Reduced Region Proposal Network and Multi-Pooling. ICASSP (2020)
Lien-Chih Hsu, Ching-Te Chiu, Kuan-Ting Lin, Hsing-Huan Chou, Yen-Yu Pu
ESSA: An energy-Aware bit-Serial streaming deep convolutional neural network accelerator. J. Syst. Archit. 111 (2020)
Ching-Chen Wang, Ching-Te Chiu, Jheng-Yi Chang
EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search. CoRR (2020)
Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, Li-Wei Wang
Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. ICASSP (2020)
Hsing-Hung Chou, Ching-Te Chiu, Yi-Ping Liao
Deep Neural Network Compression with Knowledge Distillation Using Cross-Layer Matrix, KL Divergence and Offline Ensemble. APSIPA (2020)
Meng-Chieh Wu, Ching-Te Chiu, Kun-Hsuan Wu
Multi-teacher Knowledge Distillation for Compressed Video Action Recognition on Deep Neural Networks. ICASSP (2019)
Kuan-Hung Shih, Ching-Te Chiu, Yen-Yu Pu
Real-time Object Detection via Pruning and a Concatenated Multi-feature Assisted Region Proposal Network. ICASSP (2019)
Lien-Chih Hsu, Ching-Te Chiu, Kuan-Ting Lin
An Energy-Aware Bit-Serial Streaming Deep Convolutional Neural Network Accelerator. ICIP (2019)
Ting-Yun Hsiao, Yung-Chang Chang, Hsin-Hung Chou, Ching-Te Chiu
Filter-based deep-compression with global average pooling for convolutional networks. J. Syst. Archit. 95 (2019)
Pei-Yin Chou, Ching-Te Chiu
PVDC: A Binary Descriptor Using Pore-Valley Disk Code Structure for High-Resolution Partial Fingerprint Recognition. ICASSP (2018)
Ting-Yun Hsiao, Yung-Chang Chang, Ching-Te Chiu
Filter-based Deep-Compression with Global Average Pooling for Convolutional Networks. SiPS (2018)
Jen-Wen Wang, Ching-Te Chiu
Video Super-resolution using Edge-based Optical Flow and Intensity Prediction. J. Signal Process. Syst. 90 (12) (2018)
Huai-Mao Weng, Ching-Te Chiu
Resource Efficient Hardware Implementation for Real-Time Traffic Sign Recognition. ICASSP (2018)
Shen-Li Lo, Ching-Te Chiu
Single image super-resolution using hybrid patch search and local self-similarity. ISCAS (2017)
Jou Lin, Ching-Te Chiu
Low-complexity face recognition using contour-based binary descriptor. IET Image Process. 11 (12) (2017)
Yi-Chan Wu, Ching-Te Chiu
Motion clustering with hybrid-sample-based foreground segmentation for moving cameras. ICASSP (2017)
Chen-Jung Wu, Ching-Te Chiu
Dry fingerprint detection for multiple image resolutions using ridge features. SiPS (2017)
Jou Lin, Ching-Te Chiu
LBP edge-mapped descriptor using MGM interest points for face recognition. ICASSP (2017)
Yu-Fu Mai, Ching-Te Chiu
Patch-based HDR video processing for fast moving object reconstruction. ICNC (2017)
Tsai-Te Chu, Ching-Te Chiu
A cost-effective minutiae disk code for fingerprint recognition and its implementation. ICASSP (2016)
Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu
Binary descriptor based SIFT and hardware implementation. ISCAS (2016)
Chu-Chiao Liao, Ching-Te Chiu
Fingerprint recognition with ridge features and minutiae on distortion. ICASSP (2016)
Yi-Kang Shen, Ching-Te Chiu
Local binary pattern orientation based face recognition. ICASSP (2015)
Yen Wen Chien, Ching-Te Chiu, I-Zan Wu
A real-time embedded system for human gait analysis. SiPS (2015)
Tsun-Hsien Wang, Jen-Wen Wang, Ching-Te Chiu
Virtual HDR/LDR image synthesizer in multi-core platform. GlobalSIP (2015)
Pin Yi Tsai, Yarsun Hsu, Ching-Te Chiu, Tsai-Te Chu
Accelerating AdaBoost algorithm using GPU for multi-object recognition. ISCAS (2015)
Tsun-Hsien Wang, Cheng-Wen Chiu, Wei-Chen Wu, Jen-Wen Wang, Chun-Yi Lin, Ching-Te Chiu, Jing-Jia Liou
Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment. IEEE Trans. Multim. 17 (4) (2015)
Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu
Edge Curve Scaling and Smoothing with Cubic Spline Interpolation for Image Up-Scaling. J. Signal Process. Syst. 78 (1) (2015)
Ching-Te Chiu, Lei Wang, Yin-Tsung Hwang
Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement. J. Signal Process. Syst. 78 (1) (2015)
Yao-Tsung Yang, Ching-Te Chiu
Boosted multi-class object detection with parallel hardware implementation for real-time applications. ICASSP (2014)
Jen-Wen Wang, Ching-Te Chiu
Edge-based motion and intensity prediction for video super-resolution. GlobalSIP (2014)
Loyon Kuo, Tsun-Hsien Wang, Ching-Te Chiu
Gradient-based image up-scaling with local self similarity. GlobalSIP (2014)
Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, Ching-Te Chiu
Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements. VLSI-DAT (2014)
Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu
Object recognition using bag of words with kernels for big data. ICCE-TW (2014)
Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Jen-Ming Wu, Ching-Te Chiu, Shawn S. H. Hsu, Mau-Chung Frank Chang
A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
I-Cheng Tsai, Ching-Te Chiu
Depth-based posture recognition by radar and vision fusion for real-time applications. ICASSP (2013)
Ying-Fang Tsao, Wen-Te Liu, Ching-Te Chiu
Human gait analysis by body segmentation and center of gravity. APSIPA (2013)
Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S. H. Hsu, Yang-Syu Lin, Fanta Chen, Min-Sheng Kao, Yarsun Hsu
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 21 (8) (2013)
Wei-Chih Lai, Ching-Te Chiu
Data Center Switch for Load Balanced Fat-Trees. J. Signal Process. Syst. 71 (3) (2013)
Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu
Edge curve scaling and smoothing with cubic spline interpolation. ICIP (2013)
Ching-Te Chiu, Wen-Chih Huang, Chih-Hsing Lin, Wei-Chih Lai, Ying-Fang Tsao
Embedded Transition Inversion Coding With Low Switching Activity for Serial Links. IEEE Trans. Very Large Scale Integr. Syst. 21 (10) (2013)
Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu
Edge curve scaling and smoothing with cubic spline interpolation for image upscaling. SiPS (2013)
Li Lin, Ching-Te Chiu
Low cost illumination invariant face recognition by down-up sampling self quotient image. APSIPA (2013)
Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2012)
Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yarsun Hsu
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. J. Signal Process. Syst. 66 (1) (2012)
Yung-Chang Chang, Ching-Te Chiu
A Study of NoC Topologies and Switching Arbitration Mechanisms. HPCC-ICESS (2012)
Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao
A novel low gate-count serializer topology with Multiplexer-Flip-Flops. ISCAS (2012)
Wei-Chiu Liu, Zhan-Yao Gu, Yarsun Hsu, Ching-Te Chiu
Cluster-Based CAN with Enhanced Transmission Capability for Vehicle Networks. ICCVE (2012)
Wei-Chih Lai, Ching-Te Chiu
A 5.8 Gbps uniform mapping data center switch. ICASSP (2012)
Sih-Kai Li, Jen-Shun Yang, Ching-Te Chiu, Po-Ting Yeh, Jenq-Neng Hwang
Handover Delay Reduction and Buffer-Based Data Recovery Scheme for Inter Multicast Broadcast Service Zone. GLOBECOM (2011)
Tsun-Hsien Wang, Ching-Te Chiu
Low visual difference virtual high dynamic range image synthesizer from a single legacy image. ICIP (2011)
Ruei-Jiun Wang, Ching-Te Chiu
Saliency prediction using scene motion for JND based video compression. SiPS (2011)
Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ASP-DAC (2011)
Wei-Ming Ke, Chih-Rung Chen, Ching-Te Chiu
BiTA/SWCE: Image Enhancement With Bilateral Tone Adjustment and Saliency Weighted Contrast Enhancement. IEEE Trans. Circuits Syst. Video Technol. 21 (3) (2011)
Wen-Chih Huang, Chih-Hsing Lin, Ching-Te Chiu
Embedded transition inversion coding for low power serial link. SiPS (2011)
Ching-Te Chiu, Cyuan-Jhe Wu
Texture classification based low order local binary pattern for face recognition. ICIP (2011)
Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. ISCAS (2011)
Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu
Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. J. Signal Process. Syst. 64 (1) (2011)
Chih-Rung Chen, Wei-Su Wong, Ching-Te Chiu
Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction. IEEE Trans. Very Large Scale Integr. Syst. 19 (11) (2011)
Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu
On the design and analysis of fault tolerant NoC architecture using spare routers. ASP-DAC (2011)
Chih-Rung Chen, Ching-Te Chiu
Curve-based and image-based JND contrast analysis for inverse tone mapping operators. ICIP (2011)
Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu
A novel MUX-FF circuit for low power and high speed serial link interfaces. ISCAS (2010)
Chih-Hsing Lin, Yung-Chang Chang, Wen-Chih Huang, Wei-Chih Lai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Chun-Ming Huang, Chih-Chyau Yang, Shih-Lun Chen
A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification. ISCAS (2010)
Wei-Ming Ke, Ching-Te Chiu
Hardware-efficient image enhancement with bilateral tone adjustment. ISCAS (2010)
Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ISCAS (2010)
Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu
Switching bilateral filter with a texture/noise detector for universal noise removal. ICASSP (2010)
Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu
Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal. IEEE Trans. Image Process. 19 (9) (2010)
Wei-Su Wong, Chih-Rung Chen, Ching-Te Chiu
A 100MHz hardware-efficient boost cascaded face detection design. ICIP (2009)
Wei-Ming Ke, Tsun-Hsien Wang, Ching-Te Chiu
Hardware-efficient virtual high dynamic range image reproduction. ICIP (2009)
Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 17 (5) (2009)
Chih-Hsing Lin, Ching-Te Chiu
A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias. ICECS (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Ching-Te Chiu