Boosted multi-class object detection with parallel hardware implementation for real-time applications.
Yao-Tsung YangChing-Te ChiuPublished in: ICASSP (2014)
Keyphrases
- hardware implementation
- pipelined architecture
- dedicated hardware
- real time
- fpga implementation
- multi class object detection
- fpga device
- general purpose processors
- parallel architecture
- efficient implementation
- signal processing
- processing elements
- software implementation
- fpga technology
- hardware design
- field programmable gate array
- parallel processing
- graphics processing units
- hardware architecture
- shared memory
- low cost
- general purpose
- neural network
- supervised learning
- object detection
- multi class
- pattern recognition
- three dimensional
- data sets