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A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology.
Min-Sheng Kao
Jen-Ming Wu
Chih-Hsing Lin
Fanta Chen
Ching-Te Chiu
Shawn S. H. Hsu
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2009)
Keyphrases
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cmos technology
low power
high speed
low voltage
spl times
power consumption
parallel processing
input output
power dissipation
image sensor
low cost
file system
digital images
hardware and software
external memory
hidden markov models
main memory
design process