Min-Sheng Kao

Publication Activity (10 Years)

Years Active: 2005-2014
Publications (10 Years): 0

Top Topics

Cmos Technology

Gigabit Ethernet

Reconfigurable Architecture

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

J. Signal Process. Syst.

Publications

Min-Sheng Kao, Fanta Chen, Yu-Hao Hsu, Jen-Ming Wu
20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Jen-Ming Wu, Ching-Te Chiu, Shawn S. H. Hsu, Mau-Chung Frank Chang
A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S. H. Hsu, Yang-Syu Lin, Fanta Chen, Min-Sheng Kao, Yarsun Hsu
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 21 (8) (2013)
Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yarsun Hsu
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. J. Signal Process. Syst. 66 (1) (2012)
Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ASP-DAC (2011)
Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. ISCAS (2011)
Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ISCAS (2010)
Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 17 (5) (2009)
Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. ISCAS (2008)
Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. ISCAS (2007)
Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. ASP-DAC (2007)
Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Chih-Hsien Jen, Yarsun Hsu
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology. SoCC (2005)