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A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations.

Fan-Wei YuBo-Han ZengYu-Hung HuangHsin-I WuChe-Rung LeeRen-Song Tsay
Published in: DATE (2013)
Keyphrases
  • instruction set
  • floating point
  • database
  • computer architecture
  • level parallelism
  • embedded systems
  • application specific