Satyamurthy Pullela

Publication Activity (10 Years)

Years Active: 1993-1998
Publications (10 Years): 0

Publications

Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE (1998)
Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela
Microprocessors. J. VLSI Signal Process. 16 (2-3) (1997)
Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD (1997)
Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (2) (1997)
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
Library-less synthesis for static CMOS combinational logic circuits. ICCAD (1997)
Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (6) (1996)
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC (1995)
Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (12) (1994)
Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
RC interconnect synthesis-a moment fitting approach. ICCAD (1994)
Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC (1993)