CMOS Combinational Circuit Sizing by Stage-wise Tapering.

Satyamurthy Pullela Rajendran Panda Abhijit Dharchoudhury Gopal Vija

Published in: DATE (1998)

Keyphrases

circuit design
high speed
analog vlsi
delay insensitive
asynchronous circuits
logic circuits
cmos technology
vlsi circuits
low power
power consumption
low voltage
chip design
low cost
analog circuits
power dissipation
power supply
digital circuits
real time
single phase
pairwise