Abhijit Dharchoudhury

Publication Activity (10 Years)

Years Active: 1992-1999
Publications (10 Years): 0

Publications

Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC (1999)
Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design (1999)
Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE (1998)
David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
Emerging power management tools for processor design. ISLPED (1998)
Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC (1998)
Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC (1998)
Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD (1997)
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
Library-less synthesis for static CMOS combinational logic circuits. ICCAD (1997)
Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. DAC (1996)
Abhijit Dharchoudhury, Sung-Mo Kang
Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (4) (1995)
Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ICCAD (1994)
Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel
Fast timing simulation of transient faults in digital circuits. ICCAD (1994)
Abhijit Dharchoudhury, Sung-Mo Kang
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. DAC (1993)
Abhijit Dharchoudhury, S. M. Kang
Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis. VLSI Design (1992)
Abhijit Dharchoudhury, Sung-Mo Kang
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. DAC (1992)