Alexey Glebov

Publication Activity (10 Years)

Years Active: 1995-2009
Publications (10 Years): 0

Publications

Alexander L. Stempkovsky, Alexey Glebov, Sergey Gavrilov
Calculation of stress probability for NBTI-aware timing analysis. ISQED (2009)
Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda
Delay noise pessimism reduction by logic correlations. ICCAD (2004)
Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
False-Noise Analysis for Domino Circuits. DATE (2004)
D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel
SOI Transistor Model for Fast Transient Simulation. ICCAD (2003)
Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Vladimir Zolotov
False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7 (3) (2002)
Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh
False-Noise Analysis Using Resolution Method. ISQED (2002)
Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov
False-Noise Analysis using Logic Implications. ICCAD (2001)
Sergey Gavrilov, Alexey Glebov, S. Rusakov, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan
Fast power loss calculation for digital static CMOS circuits. ED&TC (1997)
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
Library-less synthesis for static CMOS combinational logic circuits. ICCAD (1997)
Alexey Glebov, David T. Blaauw, Larry G. Jones
Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD (1995)