Transistor reordering for low power CMOS gates using an SP-BDD representation.
Alexey GlebovDavid T. BlaauwLarry G. JonesPublished in: ISLPD (1995)
Keyphrases
- low power
- high speed
- logic circuits
- power consumption
- low cost
- single chip
- high power
- cmos technology
- wireless transmission
- digital signal processing
- power dissipation
- image sensor
- vlsi circuits
- binary decision diagrams
- vlsi architecture
- mixed signal
- real time
- power reduction
- delay insensitive
- gate array
- low power consumption
- ultra low power