Florentin Dartu

Publication Activity (10 Years)

Years Active: 1993-2013
Publications (10 Years): 0

Top Topics

Hierarchical Organization

Top Venues

Publications

Florentin Dartu, Qiuyang Wu
To do or not to do hierarchical timing? ISPD (2013)
Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (3) (2010)
Kenneth S. Stevens, Florentin Dartu
Algorithms for MIS vector generation and pruning. ICCAD (2006)
Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
Weibull-based analytical waveform model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (8) (2005)
Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
Expanding the frequency range of AWE via time shifting. ICCAD (2005)
Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
Piece-wise approximations of RLCK circuit responses using moment matching. DAC (2005)
Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
Statistical static timing analysis: how simple can we get? DAC (2005)
Florentin Dartu, Anirudh Devgan, Noel Menezes
Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI (2005)
Aseem Agarwal, Florentin Dartu, David T. Blaauw
Statistical gate delay model considering multiple input switching. DAC (2004)
Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
Modeling unbuffered latches for timing analysis. ICCAD (2004)
Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
Weibull Based Analytical Waveform Model. ICCAD (2003)
Seung Hoon Choi, Kaushik Roy, Florentin Dartu
Timed pattern generation for noise-on-delay calculation. DAC (2002)
Emrah Acar, Florentin Dartu, Lawrence T. Pileggi
TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (5) (2002)
Florentin Dartu, Lawrence T. Pileggi
TETA: Transistor-Level Engine for Timing Analysis. DAC (1998)
Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
CMOS Gate Delay Models for General RLC Loading. ICCD (1997)
Florentin Dartu, Lawrence T. Pileggi
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC (1997)
Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi
An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC (1996)
Florentin Dartu, Noel Menezes, Lawrence T. Pileggi
Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (5) (1996)
Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi
RC-Interconnect Macromodels for Timing Simulation. DAC (1996)
Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
RC interconnect synthesis-a moment fitting approach. ICCAD (1994)
Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
A Gate-Delay Model for high-Speed CMOS Circuits. DAC (1994)
Ion Constatin Tesu, Florentin Dartu
Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits. ISCAS (1993)