Ravishankar Arunachalam

Publication Activity (10 Years)

Years Active: 1997-2005
Publications (10 Years): 0

Publications

Aniket, Ravishankar Arunachalam
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. VLSI Design (2005)
Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam
Static Transition Probability Analysis Under Uncertainty. ICCD (2004)
Emrah Acar, Ravishankar Arunachalam, Sani R. Nassif
Predicting short circuit power from timing models. ASP-DAC (2003)
Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif
Optimal shielding/spacing metrics for low power design. ISVLSI (2003)
Ravishankar Arunachalam, Ronald DeShawn Blanton, Lawrence T. Pileggi
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation. VLSI Design 2002 (3) (2002)
Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
False Coupling Interactions in Static Timing Analysis. DAC (2001)
Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
TACO: timing analysis with coupling. DAC (2000)
Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
Determination of worst-case aggressor alignment for delay calculation. ICCAD (1998)
Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
CMOS Gate Delay Models for General RLC Loading. ICCD (1997)