Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.

Noel Menezes Satyamurthy Pullela Lawrence T. Pileggi

Published in: DAC (1995)

Keyphrases

power dissipation
high speed
cmos technology
low power
neural network
constrained optimization
data sets
learning algorithm
linear programming
levels of abstraction
real time
optimization problems
steady state
optimization method
global optimization