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Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.

Satyamurthy PullelaNoel MenezesLawrence T. Pileggi
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1997)
Keyphrases
  • high speed
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  • solid models
  • power consumption
  • programmable logic