Min Zhao

Publication Activity (10 Years)

Years Active: 1998-2010
Publications (10 Years): 0

Publications

Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (9) (2010)
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
Power Grid Analysis and Optimization Using Algebraic Multigrid. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED (2008)
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD (2007)
Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC (2007)
Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao
A novel technique for incremental analysis of on-chip power distribution networks. ICCAD (2007)
Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC (2006)
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power-supply pads and pins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (1) (2006)
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
Fast decap allocation based on algebraic multigrid. ICCAD (2006)
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
Timing driven track routing considering coupling capacitance. ASP-DAC (2005)
V. Seth, Min Zhao, Jiang Hu
Exploiting level sensitive latches in wire pipelining. ICCAD (2004)
Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao
Layer assignment for crosstalk risk minimization. ASP-DAC (2004)
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power supply pads and pins. DAC (2004)
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) (2003)
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (1) (2003)
Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda
Statistical delay computation considering spatial correlations. ASP-DAC (2003)
Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems (2002)
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (2) (2002)
Min Zhao, Sachin S. Sapatnekar
Technology mapping algorithms for domino logic. ACM Trans. Design Autom. Electr. Syst. 7 (2) (2002)
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
A precorrected-FFT method for simulating on-chip inductance. ICCAD (2002)
Min Zhao, Sachin S. Sapatnekar
A New Structural Pattern Matching Algorithm for Technology Mapping. DAC (2001)
Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
Inductance 101: Analysis and Design Issues. DAC (2001)
Min Zhao, Sachin S. Sapatnekar
Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. ISCAS (2000)
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw
Hierarchical analysis of power distribution networks. DAC (2000)
Min Zhao, Sachin S. Sapatnekar
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (11) (2000)
Min Zhao, Sachin S. Sapatnekar
Timing-driven partitioning for two-phase domino and mixed static/domino implementations. ICCAD (1999)
Min Zhao, Sachin S. Sapatnekar
Technology mapping for domino logic. ICCAD (1998)