Can Sitik

Publication Activity (10 Years)

Years Active: 2012-2019
Publications (10 Years): 8

Top Topics

Design Methodology

Top Venues

ACM Great Lakes Symposium on VLSI

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang
SLECTS: Slew-Driven Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
Low Voltage Clock Tree Synthesis with Local Gate Clusters. ACM Great Lakes Symposium on VLSI (2019)
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
Exploiting useful skew in gated low voltage clock trees. ISCAS (2016)
Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman
Design Methodology for Voltage-Scaled Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 24 (10) (2016)
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. ACM Great Lakes Symposium on VLSI (2015)
Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
Enhanced level shifter for multi-voltage operation. ISCAS (2015)
Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin
A Novel Static D-Flip-Flop Topology for Low Swing Clocking. ACM Great Lakes Symposium on VLSI (2015)
Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin
FinFET-Based Low-Swing Clocking. ACM J. Emerg. Technol. Comput. Syst. 12 (2) (2015)
Can Sitik, Leo Filippini, Emre Salman, Baris Taskin
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. ISVLSI (2014)
Can Sitik, Scott Lerner, Baris Taskin
Timing characterization of clock buffers for clock tree synthesis. ICCD (2014)
Can Sitik, Baris Taskin
Iterative skew minimization for low swing clocks. Integr. 47 (3) (2014)
Can Sitik, Baris Taskin
Skew-bounded low swing clock tree optimization. ACM Great Lakes Symposium on VLSI (2013)
Can Sitik, Prawat Nagvajara, Baris Taskin
A microcontroller-based embedded system design course with PSoC3. MSE (2013)
Can Sitik, Baris Taskin
Multi-corner multi-voltage domain clock mesh design. ACM Great Lakes Symposium on VLSI (2013)
Can Sitik, Baris Taskin
Multi-voltage domain clock mesh design. ICCD (2012)