Low Voltage Clock Tree Synthesis with Local Gate Clusters.

Can Sitik Weicheng Liu Baris Taskin Emre Salman

Published in: ACM Great Lakes Symposium on VLSI (2019)

Keyphrases

low voltage
cmos technology
leakage current
power consumption
low power
power line
high speed
clustering algorithm
tree structure
design considerations
power management
power dissipation
hierarchical structure
leaf nodes
energy efficiency
parallel processing
image processing
e learning