Scott Lerner

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 13

Top Topics

Design Automation

Genetic Algorithm

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin
Design Automation for Charge Recovery Logic. ISCAS (2024)
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano
Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (4) (2021)
Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin
Low Swing - Low Frequency Rotary Traveling Wave Oscillators. ISCAS (2019)
Scott Lerner, Baris Taskin
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Scott Lerner, Isikcan Yilmaz, Baris Taskin
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis
Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED (2019)
Scott Lerner, Vasil Pano, Baris Taskin
NoC Router Lifetime Improvement using Per-Port Router Utilization. ISCAS (2018)
Scott Lerner, Baris Taskin
Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis. IGSC (2018)
Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin
Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. ISCAS (2018)
Scott Lerner, Eric Leggett, Baris Taskin
Slew-down: analysis of slew relaxation for low-impact clock buffers. SLIP (2017)
Scott Lerner, Baris Taskin
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. ISVLSI (2017)
Scott Lerner, Baris Taskin
Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. ISQED (2017)
Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin
Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. ISCAS (2017)
Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. VLSI Design (2015)
Can Sitik, Scott Lerner, Baris Taskin
Timing characterization of clock buffers for clock tree synthesis. ICCD (2014)
Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals
A High-Speed Optical Multi-Drop Bus for Computer Interconnections. Hot Interconnects (2008)