An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.
Patrick GirardOlivier HéronSerge PravossoudovitchMichel RenovellPublished in: J. Electron. Test. (2006)
Keyphrases
- built in self test
- integrated circuit
- hardware software
- random access memory
- real time
- hardware implementation
- management system
- neural network
- fpga implementation
- hardware design
- fault detection
- fault diagnosis
- embedded systems
- power consumption
- fpga technology
- data flow
- model based diagnosis
- low power
- hardware architecture
- digital circuits
- software architecture
- fault models
- expert systems