David M. Wu

Publication Activity (10 Years)

Years Active: 1984-2006
Publications (10 Years): 0

Publications

Zhuoyu Bao, Suriya A. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin
A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors. DELTA (2006)
David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor. ITC (2004)
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. ITC (2003)
David M. Wu
Trouble With Scan. ITC (2002)
Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu
Cold Delay Defect Screening. VTS (2000)
David M. Wu
DFT is all I can afford, who cares about Design for Yield or Design for Reliability! ITC (1999)
David M. Wu
"DFY and DFR are more important than DFT". ITC (1999)
David M. Wu, Robert M. Swanson
Multiple redundancy removal during test generation and synthesis. VTS (1992)
Waisum Wong, Juin J. Liou, Jiann-Shiun Yuan, David M. Wu
Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits. VTS (1991)
Jiann-Shiun Yuan, Juin J. Liou, David M. Wu
Testing the impact of process defects on ECL power-delay performance. VTS (1991)
David M. Wu
An optimized delay testing technique for LSSD-based VLSI logic circuits. VTS (1991)
David M. Wu, Charles E. Radke
Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits. DAC (1991)
David M. Wu, Charles E. Radke, J. Paul Roth
Statistical AC Test Coverage. ITC (1986)
David M. Wu, Charles E. Radke, C. C. Beh
Improve Yield and Quality Through Testability Analysis of VLSI Circuits. ITC (1984)