Scan Cell Ordering for Low Power BIST.
Maciej BellosDimitris BakalisDimitris NikolosPublished in: ISVLSI (2004)
Keyphrases
- low power
- low cost
- power consumption
- high speed
- high power
- wireless transmission
- single chip
- logic circuits
- vlsi architecture
- vlsi circuits
- image sensor
- digital signal processing
- mixed signal
- low power consumption
- cmos technology
- power reduction
- general purpose
- rate distortion
- computer simulation
- built in self test
- gate array