Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units.
Giorgos DimitrakopoulosCostas GalanopoulosChristos MavrokefalidisDimitris NikolosPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2008)
Keyphrases
- low power
- floating point
- high speed
- logic circuits
- delay insensitive
- power consumption
- fixed point
- low cost
- high power
- single chip
- instruction set
- low power consumption
- wireless transmission
- real time
- digital signal processing
- vlsi circuits
- sparse matrices
- gate array
- mixed signal
- vlsi architecture
- cmos technology
- probabilistic model
- floating point arithmetic
- power reduction
- sufficient conditions
- bayesian networks