Sorin Cotofana

ORCID

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 35

Top Venues

CoRR

NANOARCH

DATE

ACM Great Lakes Symposium on VLSI

Publications

Abdulqader Nael Mahmoud, Florin Ciubotaru, Frederic Vanderveken, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
Two Cascaded Spin Wave Majority Gates Operation Under Continuous and Pulse Modes. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Arne Van Zegbroeck, Pantazis Anagnostou, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana
Spin Wave Threshold Gate. CoRR (2024)
Christoph Adelmann, Florin Ciubotaru, Fanfan Meng, Sorin Cotofana, Sebastien Couet
Spintronic logic: from transducers to logic gates and circuits. CoRR (2024)
Arne Van Zegbroeck, Pantazis Anagnostou, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana
Spin Wave Threshold Logic Gates. NANOARCH (2023)
Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Camsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Kang Wang, Belita Koiller, Gabriel Aguilar, Guilherme Temporão, Kremena Makasheva, Aida Tordi-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Evershor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto
Roadmap for Unconventional Computing with Nanotechnology. CoRR (2023)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Said Hamdioui, Sorin Cotofana
Spin Wave Based Approximate Computing. IEEE Trans. Emerg. Top. Comput. 10 (4) (2022)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Said Hamdioui, Sorin Cotofana
Non-Binary Spin Wave Based Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (10) (2022)
Abdulqader Nael Mahmoud, Nicoleta Cucu Laurenciu, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
Would Magnonic Circuits Outperform CMOS Counterparts? ACM Great Lakes Symposium on VLSI (2022)
He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Cotofana
Graphene-Based Artificial Synapses with Tunable Plasticity. ACM J. Emerg. Technol. Comput. Syst. 17 (4) (2021)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana
Achieving Wave Pipelining in Spin Wave Technology. ISQED (2021)
Abdulqader Nael Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotofana, Florin Ciubotaru, Said Hamdioui
Fan-out of 2 Triangle Shape Spin Wave Logic Gates. DATE (2021)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana, Said Hamdioui
Spin Wave Normalization Toward All Magnonic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
Spin Wave Based 4-2 Compressor. ICECS (2021)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
Spin Wave Based Full Adder. ISCAS (2021)
Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott
Evolutionary Bin Packing for Memory-Efficient Dataflow Inference Acceleration on FPGA. CoRR (2020)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
n-bit Data Parallel Spin Wave Logic Gate. DATE (2020)
Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott
Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA. GECCO (2020)
Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. FPT (2020)
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
Memristive oscillatory circuits for resolution of NP-complete logic puzzles: Sudoku case. CoRR (2020)
Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kelian Lin, Kun Zhang, Youguang Zhang, Xiulong Wu, Sorin Cotofana, Yue Zhang
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM. IEEE Trans. Circuits Syst. (12) (2020)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana, Said Hamdioui
2-Output Spin Wave Programmable Logic Gate. ISVLSI (2020)
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana
4-output Programmable Spin Wave Logic Gate. ICCD (2020)
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case. ISCAS (2020)
Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. CoRR (2020)
Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Cotofana
Complementary Arranged Graphene Nanoribbon-based Boolean Gates. NANOARCH (2018)
Xu He, Yao Wang, Yang Guo, Sorin Cotofana
A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance. ACM Great Lakes Symposium on VLSI (2017)
Changlin Chen, Yaowen Fu, Sorin Cotofana
Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (2) (2017)
Bo Yang, Emanuel M. Popovici, Michael Alan Quille, Andreas Amann, Sorin Cotofana
A supply voltage-dependent variation aware reliability evaluation model. NANOARCH (2016)
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana, Costin Anghel
TFET NDR skewed inverter based sensing method. NANOARCH (2016)
Thien Truong Nguyen-Ly, Tushar Gupta, Manuel Pezzin, Valentin Savin, David Declercq, Sorin Cotofana
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units. DSD (2016)
Jiaoyan Chen, Sorin Cotofana, Satish Grandhi, Christian Spagnol, Emanuel M. Popovici
Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits. Microelectron. Reliab. 55 (12) (2015)
Thomas Marconi, Sorin Cotofana
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding. ACM Great Lakes Symposium on VLSI (2015)
Alexandru Gheolbanoiu, Lucian Petrica, Sorin Cotofana
Hybrid adaptive clock management for FPGA processor acceleration. DATE (2015)
Satish Grandhi, David McCarthy, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana
ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits. ICCD (2015)
Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier. ASYNC (2015)
Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana
Robust sub-powered asynchronous logic. PATMOS (2014)
Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana
Transmission Channel Noise Aware Energy Effective LDPC Decoding. VLSI-SoC (Selected Papers) (2014)
Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana
Towards energy effective LDPC decoding by exploiting channel noise variability. VLSI-SoC (2014)
Changlin Chen, Sorin Cotofana
Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs. NoCArc@MICRO (2014)
Hillary Siewobr, Kazeem Alagbe Gbolagade, Sorin Cotofana
+ 1}. ISIC (2014)
Héctor Pettenghi, Sorin Cotofana, Leonel Sousa
± k} Multipliers. J. Circuits Syst. Comput. 23 (1) (2014)
Jiaoyan Chen, Christian Spagnol, Satish Grandhi, Emanuel M. Popovici, Sorin Cotofana, Alexandru Amaricai
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits. ISVLSI (2014)
Saleh Safiruddin, Sorin Cotofana, Ferdinand Peper
Stigmergic search with single electron tunneling technology based memory enhanced hubs. NANOARCH (2012)
Anca Mariana Molnos, Ashkan Beyranvand Nejad, Ba Thang Nguyen, Sorin Cotofana, Kees Goossens
Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms. Map2MPSoC/SCOPES (2012)
Andrew Nelson, Anca Molnos, Ashkan Beyranvand Nejad, Davit Mirzoyan, Sorin Cotofana, Kees Goossens
Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints. WESE (2012)
Jude Angelo Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink
Composable local memory organisation for streaming applications on embedded MPSoCs. Conf. Computing Frontiers (2011)
Yao Wang, Sorin Cotofana, Liang Fang
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits. NANOARCH (2011)
Kazeem Alagbe Gbolagade, Sorin Cotofana
An O(n) Residue Number System to Mixed Radix Conversion Technique. ISCAS (2009)
Marius Enachescu, Sorin Cotofana, Arjan J. van Genderen, Dimitrios Tsamados, Adrian M. Ionescu
Can SG-FET Replace FET in Sleep Mode Circuits? NanoNet (2009)
Ben Kuiper, Sorin Cotofana
Adaptive Clock Scheduling for pipelined structures. NANOARCH (2009)
Nor Zaidi Haron, Said Hamdioui, Sorin Cotofana
Emerging non-CMOS nanoelectronic devices - What are they?. NEMS (2009)
Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors. J. Signal Process. Syst. 57 (2) (2009)
Ben H. H. Juurlink, Iosif Antochi, Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis
GRAAL: A Framework for Low-Power 3D Graphics Accelerators. IEEE Computer Graphics and Applications 28 (4) (2008)
Cor Meenderinck, Sorin Cotofana
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology. SAMOS (2006)
Cor Meenderinck, Sorin Cotofana
Electron counting based high-radix multiplication in single electron tunneling technology. ISCAS (2006)
Tudor Niculiu, Cristian Lupu, Sorin Cotofana
Consciousness for modeling intelligence - simulating the evolution by closure to the inverse. ICINCO-ICSO (2006)
Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. J. VLSI Signal Process. 39 (3) (2005)
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio
CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP (2005)
Cor Meenderinck, Sorin Cotofana, Casper Lageweg
High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology. ASAP (2005)
Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ISVLSI (2004)
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
Efficient Hardware for Antialiasing Coverage Mask Generation. Computer Graphics International (2004)
Peter Celinski, Derek Abbott, Sorin Cotofana
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. PATMOS (2004)
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
Binary Multiplication based on Single Electron Tunneling. ASAP (2004)
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven
Compositional Memory Systems for Data Intensive Applications. DATE (2004)
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
High-Level Energy Estimation for ARM-Based SOCs. SAMOS (2004)
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
GRAAL - A Development Framework for Embedded Graphics Accelerators. DATE (2004)
Dan Crisu, Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha
Low cost and latency embedded 3D graphics reciprocation. ISCAS (2) (2004)
Peter Celinski, Sorin Cotofana, Derek Abbott
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. IWANN (2) (2003)
Marius Padure, Sorin Cotofana, Stamatis Vassiliadis
Design and experimental results of a CMOS flip-flop featuring embedded threshold logic. ISCAS (5) (2003)
Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
Microcode Processing: Positioning and Directions. IEEE Micro 23 (4) (2003)
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. VLSI-SoC (Selected Papers) (2003)
Marius Padure, Sorin Cotofana, Stamatis Vassiliadis
CMOS Implementation of Generalized Threshold Functions. IWANN (2) (2003)
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. VLSI-SOC (2003)
Sorin Cotofana, Casper Lageweg, Stamatis Vassiliadis
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge. IEEE Symposium on Computer Arithmetic (2003)
Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana
D-SAB: A Sparse Matrix Benchmark Suite. PaCT (2003)
Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana
A Hierarchical Sparse Matrix Storage Format for Vector Processors. IPDPS (2003)
Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven
Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor. ASAP (2003)
Marius Padure, Sorin Cotofana, Stamatis Vassiliadis, Claudius Dan, Mircea Bodea
A low-power threshold logic family. ICECS (2002)
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. FCCM (2002)
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
A Sum of Absolute Differences Implementation in FPGA Hardware. EUROMICRO (2002)
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
A full adder implementation using SET based linear threshold gates. ICECS (2002)
Tudor Niculiu, Sorin Cotofana
Hierarchical Intellignet Mixed Simulation. ESM (2002)
Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers
Field-Programmable Custom Computing Machines - A Taxonomy -. FPL (2002)
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
Microcoded Reconfigurable Embedded Processors: Current Developments. Embedded Processor Design Challenges (2002)
Stephan Wong, Bastiaan Stougie, Sorin Cotofana
Alternatives in FPGA-based SAD implementations. FPT (2002)
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. Embedded Processor Design Challenges (2002)
Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia. FCCM (2001)
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. ICCD (2001)
Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
The MOLEN rho-mu-Coded Processor. FPL (2001)
Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
Coarse Reconfigurable Multimedia Unit Extension. PDP (2001)
Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana
Topic 15+20: Multimedia and Embedded Systems. Euro-Par (2001)
Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
Multimedia Enhanced General-Purpose Processors. IEEE International Conference on Multimedia and Expo (III) (2000)
Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, Henk Corporaal
Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note). Euro-Par (2000)
Tudor Niculiu, Chouki Aktouf, Sorin Cotofana
Hierarchical interfaces for hardware software systems. ESM (2000)
Sorin Cotofana, Stamatis Vassiliadis
Signed Digit Addition and Related Operations with Threshold Logic. IEEE Trans. Computers 49 (3) (2000)
Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis
Counter Based Superscalar Instruction Issuing. EUROMICRO (2000)
Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
General-Purpose Processor Huffman Encoding Extension. ITCC (2000)
Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis
Vector ISA Extension for Sparse Matrix-Vector Multiplication. Euro-Par (1999)
Sorin Cotofana, Stamatis Vassiliadis
Serial binary multiplication with feed-forward neural networks. Neurocomputing 28 (1-3) (1999)
Sorin Cotofana, Stamatis Vassiliadis
Periodic symmetric functions, serial addition, and multiplication with neural networks. IEEE Trans. Neural Networks 9 (6) (1998)

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Publication Activity (10 Years)

Top Topics

Top Venues

Sorin Cotofana