A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.

Peter Celinski Sorin Cotofana Derek Abbott

Published in: IWANN (2) (2003)

Keyphrases

high speed
low power
random access memory
logic circuits
shift register
low cost
data flow
delay insensitive
dynamic environments
real time
focal plane
power dissipation
chip design
vlsi circuits
logical operations
predicate logic
multi valued
image processing