Hybrid adaptive clock management for FPGA processor acceleration.
Alexandru GheolbanoiuLucian PetricaSorin CotofanaPublished in: DATE (2015)
Keyphrases
- high speed
- fpga device
- single chip
- ibm zenterprise
- management system
- information systems
- xilinx virtex
- digital signal
- hardware implementation
- gate array
- parallel architecture
- parallel processing
- power consumption
- data management
- low power
- field programmable gate array
- data processing
- knowledge management
- low cost
- information management
- data acquisition
- decision support
- software implementation
- resource manager
- decision making
- real time