Yue Zhang

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 34

Top Topics

Design Space Exploration

Reinforcement Learning

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Microelectron. Reliab.

Publications

Yanjie Song, Ponnuthurai Nagaratnam Suganthan, Witold Pedrycz, Ran Yan, Dongming Fan, Yue Zhang
Energy-Efficient Satellite Range Scheduling Using a Reinforcement Learning-Based Memetic Algorithm. IEEE Trans. Aerosp. Electron. Syst. 60 (4) (2024)
Yanjie Song, Yutong Wu, Yangyang Guo, Ran Yan, Ponnuthurai Nagaratnam Suganthan, Yue Zhang, Witold Pedrycz, Swagatam Das, Rammohan Mallipeddi, Oladayo Solomon Ajani, Qiang Feng
Reinforcement learning-assisted evolutionary algorithm: A survey and research opportunities. Swarm Evol. Comput. 86 (2024)
Jinkai Wang, Zhengkun Gu, Bojun Zhang, Youxiang Chen, Zekun Wang, Kun Zhang, Youguang Zhang, Yue Zhang
RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (3) (2024)
Kaili Zhang, Zhongzhen Tong, Xinxin Liang, Chengzhi Wang, You Wang, Yue Zhang, Weisheng Zhao, Lang Zeng, Deming Zhang
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Yanjie Song, Junwei Ou, Witold Pedrycz, Ponnuthurai Nagaratnam Suganthan, Xinwei Wang, Lining Xing, Yue Zhang
Generalized Model and Deep Reinforcement Learning-Based Evolutionary Method for Multitype Satellite Observation Scheduling. IEEE Trans. Syst. Man Cybern. Syst. 54 (4) (2024)
Zhipeng Guo, Deming Zhang, Kaili Zhang, Mingyang Song, Yue Zhang, Lang Zeng
A Novel Search-Based Compute-in-Memory Minimum Values Generation Scheme for Low-Complexity LDPC Min-Sum Decoding. IEEE Trans. Circuits Syst. II Express Briefs 71 (7) (2024)
Shiyu Liu, Jun Wang, Rui Wang, Yue Zhang, Yanjie Song, Lining Xing
Data-driven dynamic pricing and inventory management of an omni-channel retailer in an uncertain demand environment. Expert Syst. Appl. 244 (2024)
Yanjie Song, Yutong Wu, Yangyang Guo, Ran Yan, Ponnuthurai N. Suganthan, Yue Zhang, Witold Pedrycz, Yingwu Chen, Swagatam Das, Rammohan Mallipeddi, Oladayo Solomon Ajani
Reinforcement Learning-assisted Evolutionary Algorithm: A Survey and Research Opportunities. CoRR (2023)
Kaili Zhang, Deming Zhang, Mingyang Song, Zhipeng Guo, You Wang, Chengzhi Wang, Yue Zhang, Lang Zeng
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Jinkai Wang, Yining Bai, Hongyu Wang, Zuolei Hao, Guanda Wang, Kun Zhang, Youguang Zhang, Weifeng Lv, Yue Zhang
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Nikolaos Vasileiadis, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis, Yue Zhang, Ioannis G. Karafyllidis
Memristor Crossbar Arrays Performing Quantum Algorithms. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (2) (2022)
Yue Zhang, Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kun Zhang, Georgios Ch. Sirakoulis, Youguang Zhang
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Yining Bai, Yue Zhang, Jinkai Wang, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Kun Zhang, Weisheng Zhao
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM. ACM Great Lakes Symposium on VLSI (2020)
Jiang Nan, Kun Zhang, Yue Zhang, Shaohua Yan, Zhizhong Zhang, Zhenyi Zheng, Guanda Wang, Qunwen Leng, Youguang Zhang, Weisheng Zhao
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic. IEEE Access 8 (2020)
Zhe Huang, Yue Zhang, Kun Zhang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang, Weisheng Zhao
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device. ACM Great Lakes Symposium on VLSI (2020)
Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kelian Lin, Kun Zhang, Youguang Zhang, Xiulong Wu, Sorin Cotofana, Yue Zhang
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM. IEEE Trans. Circuits Syst. (12) (2020)
Jinkai Wang, Yue Zhang, Chenyu Lian, Yining Bai, Zhe Huang, Guanda Wang, Kun Zhang, Youguang Zhang, Weisheng Zhao
Efficient Time-Domain In-Memory Computing Based on TST-MRAM. ISCAS (2020)
Yue Zhang, Jiang Nan, Guanda Wang, Xueying Zhang, Youguang Zhang, Weisheng Zhao
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions. NANOARCH (2019)
Jinkai Wang, Yue Zhang, Chenyu Lian, Guanda Wang, Kun Zhang, Xiulong Wu, Youguang Zhang, Weisheng Zhao
High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM. NANOARCH (2019)
Guanda Wang, Yue Zhang, Beibei Zhang, Bi Wu, Jiang Nan, Xueying Zhang, Zhizhong Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Guanda Wang, Yue Zhang, Zhe Huang, Jinkai Wang, Kun Zhang, Zhizhong Zhang, Youguang Zhang, Weisheng Zhao
Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction. NANOARCH (2019)
You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning. ACM Great Lakes Symposium on VLSI (2018)
Guanda Wang, Yue Zhang, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction. NANOARCH (2017)
Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao
A true random number generator based on parallel STT-MTJs. DATE (2017)
Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy. NANOARCH (2016)
Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2016)
Y. Wang, Hao Cai, Lirida A. B. Naviner, X. X. Zhao, Yue Zhang, Mariem Slimani, Jacques-Olivier Klein, Weisheng Zhao
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI. Microelectron. Reliab. 64 (2016)
Deming Zhang, Lang Zeng, Kaihua Cao, Mengxing Wang, Shouzhong Peng, Yue Zhang, Youguang Zhang, Jacques-Olivier Klein, Yu Wang, Weisheng Zhao
All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron. IEEE Trans. Biomed. Circuits Syst. 10 (4) (2016)
Yue Zhang, Chao Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system. ISCAS (2015)
Y. Wang, Hao Cai, Lirida A. B. Naviner, Yue Zhang, Jacques-Olivier Klein, Weisheng Zhao
Compact thermal modeling of spin transfer torque magnetic tunnel junction. Microelectron. Reliab. 55 (9-10) (2015)
Mengxing Wang, Yue Zhang, Xiaoxuan Zhao, Weisheng Zhao
Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges. Micromachines 6 (8) (2015)
Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. ACM J. Emerg. Technol. Comput. Syst. 12 (2) (2015)
Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang
From device to system: cross-layer design exploration of racetrack memory. DATE (2015)
Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires. NANOARCH (2014)
Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2014)
Djaafar Chabi, Weisheng Zhao, Erya Deng, Yue Zhang, Nesrine Ben Romdhane, Jacques-Olivier Klein, Claude Chappert
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
You Wang, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Lirida A. B. Naviner, Weisheng Zhao
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses. Microelectron. Reliab. 54 (9-10) (2014)
Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert
An overview of spin-based integrated circuits. ASP-DAC (2014)
Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert
Spintronics for low-power computing. DATE (2014)
Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. 74 (6) (2014)
Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert
Spin-electronics based logic fabrics. VLSI-SoC (2013)
Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
Synchronous full-adder based on complementary resistive switching memory cells. NEWCAS (2013)
Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein, Yue Zhang, Dafine Ravelosona, Claude Chappert
Magnetic Adder Based on Racetrack Memory. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2013)
Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao
Analytical study of complementary memristive synchronous logic gates. NANOARCH (2013)
Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. Microelectron. Reliab. 53 (9-11) (2013)
Djaafar Chabi, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Claude Chappert
Low power magnetic flip-flop based on checkpointing and self-enable mechanism. NEWCAS (2013)
Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
Crossbar architecture based on 2R complementary resistive switching memory cell. NANOARCH (2012)
Weisheng Zhao, Yue Zhang, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer
Failure and reliability analysis of STT-MRAM. Microelectron. Reliab. 52 (9-10) (2012)
Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli
Embedded MRAM for high-speed computing. VLSI-SoC (2011)
Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert
High Performance SoC Design Using Magnetic Logic and Memory. VLSI-SoC (Selected Papers) (2011)