Daniel Etiemble

Publication Activity (10 Years)

Years Active: 1977-2023
Publications (10 Years): 19

Top Topics

Connected Component Labeling

Computing Paradigms

Top Venues

J. Real Time Image Process.

Int. J. Parallel Program.

Publications

Thomas Romera, Andrea Petreto, Florian Lemaitre, Manuel Bouyer, Quentin L. Meunier, Lionel Lacassagne, Daniel Etiemble
Optical flow algorithms optimized for speed, energy and accuracy on embedded GPUs. J. Real Time Image Process. 20 (2) (2023)
Daniel Etiemble
CNTFET quaternary multipliers are less efficient than the corresponding binary ones. CoRR (2022)
Daniel Etiemble
Ternary and Quaternary CNTFET Full Adders are less efficient than the Binary Ones for Carry-Propagate Adders. CoRR (2022)
Daniel Etiemble
Technologies and Computing Paradigms: Beyond Moore's law? CoRR (2022)
Daniel Etiemble
Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders. CoRR (2022)
Daniel Etiemble
Best CNTFET Ternary Adders? CoRR (2021)
Daniel Etiemble
Multivalued circuits and Interconnect issues. CoRR (2020)
Daniel Etiemble
Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits". IEEE Access 8 (2020)
Daniel Etiemble
Best implementations of quaternary adders. CoRR (2020)
Daniel Etiemble
Comparing quaternary and binary multipliers. CoRR (2020)
Daniel Etiemble
Evolution of Technologies and Multivalued Circuits. CoRR (2019)
Daniel Etiemble
Comparing ternary and binary adders and multipliers. CoRR (2019)
Daniel Etiemble
Ternary circuits: why R=3 is not the Optimal Radix for Computation. CoRR (2019)
Daniel Etiemble
Coprocessors: failures and successes. CoRR (2019)
Laurent Cabaret, Lionel Lacassagne, Daniel Etiemble
Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors. J. Real Time Image Process. 15 (1) (2018)
Daniel Etiemble
45-year CPU evolution: one law and two equations. CoRR (2018)
Laurent Cabaret, Lionel Lacassagne, Daniel Etiemble
Distanceless label propagation: An efficient direct connected component labeling algorithm for GPUs. IPTA (2017)
Antoine Tran Tan, Joel Falcou, Daniel Etiemble, Hartmut Kaiser
Automatic Task-Based Code Generation for High Performance Domain Specific Embedded Language. Int. J. Parallel Program. 44 (3) (2016)
Lionel Lacassagne, Laurent Cabaret, Daniel Etiemble, Farouk Hebache, Andrea Petreto
A new SIMD iterative connected component labeling algorithm. WPMVP@PPoPP (2016)
Florence Laguzet, Andrés Romero Mier y Terán, Michèle Gouiffès, Lionel Lacassagne, Daniel Etiemble
Color tracking with contextual switching: real-time implementation on CPU. J. Real Time Image Process. 10 (2) (2015)
Laurent Cabaret, Lionel Lacassagne, Daniel Etiemble
Parallel light speed labeling: An efficient connected component labeling algorithm for multi-core processors. ICIP (2015)
Lionel Lacassagne, Daniel Etiemble, Ali Hassan Zahraee, Alain Dominguez, Pascal Vezolle
High level transforms for SIMD and low-level computer vision algorithms. WPMVP@PPoPP (2014)
H. Ye, Lionel Lacassagne, Joël Falcou, Daniel Etiemble, Laurent Cabaret, O. Florent
High level tranforms toreduce energy consumption of signal and image processing operators. PATMOS (2013)
Khaled Hamidouche, Fernando Machado Mendonca, Joel Falcou, Alba Cristina Magalhaes Alves de Melo, Daniel Etiemble
Parallel Smith-Waterman Comparison on Multicore and Manycore Computing Platforms with BSP++. Int. J. Parallel Program. 41 (1) (2013)
H. Ye, Lionel Lacassagne, Daniel Etiemble, Laurent Cabaret, Joel Falcou, Andrés Romero Mier y Terán, O. Florent
Impact of high level transforms on high level synthesis for motion detection algorithm. DASIP (2012)
Charly Bechara, Nicolas Ventroux, Daniel Etiemble
Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems. DSD (2011)
Charly Bechara, Aurelien Berhault, Nicolas Ventroux, Stéphane Chevobbe, Yves Lhuillier, Raphaël David, Daniel Etiemble
A small footprint interleaved multithreaded processor for embedded systems. ICECS (2011)
Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli
Embedded MRAM for high-speed computing. VLSI-SoC (2011)
Khaled Hamidouche, Fernando Machado Mendonca, Joël Falcou, Daniel Etiemble
Parallel Biological Sequence Comparison on Heterogeneous High Performance Computing Platforms with BSP++. SBAC-PAD (2011)
Charly Bechara, Nicolas Ventroux, Daniel Etiemble
AHDAM: An Asymmetric Homogeneous with Dynamic Allocator Manycore Chip. Facing the Multicore-Challenge (2011)
Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert
High Performance SoC Design Using Magnetic Logic and Memory. VLSI-SoC (Selected Papers) (2011)
Khaled Hamidouche, Joel Falcou, Daniel Etiemble
A framework for an automatic hybrid MPI+OpenMP code generation. SpringSim (HPC) (2011)
Florence Laguzet, Michèle Gouiffès, Lionel Lacassagne, Daniel Etiemble
Automatic color space switching for robust tracking. ICSIPA (2011)
Charly Bechara, Nicolas Ventroux, Daniel Etiemble
Towards a parameterizable cycle-accurate ISS in ArchC. AICCSA (2010)
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel Lacassagne, Daniel Etiemble
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor. PACT (2009)
Daniel Etiemble, Lionel Lacassagne
Des flottants 16 bits sur microprocesseurs d'usage général pour images et multimédia. Tech. Sci. Informatiques 24 (6) (2005)
Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kablia
16-bit Floating Point Instructions for Embedded Multimedia Applications. CAMP (2005)
Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne
Customizing 16-bit FP Instructions on a NIOS II Processor for FPGA Image and Media Processing. ESTIMedia (2005)
Daniel Etiemble, Lionel Lacassagne
16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing. ICPP (2004)
Daniel Etiemble
Why M-Valued Circuits are Restricted to a Small Niche. J. Multiple Valued Log. Soft Comput. 9 (1) (2003)
Daniel Etiemble
Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware". Theor. Comput. Sci. 279 (1-2) (2002)
Franck Cappello, Daniel Etiemble
MPI ou MPI+OpenMP sur grappes de multiprocesseurs? Tech. Sci. Informatiques 21 (2) (2002)
Daniel Etiemble
Numerical Applications and Sub-Word Parallelism: The NAS Benchmarks on a Pentium 4. HPCS (2002)
Daniel Etiemble
Optimizing DSP and media benchmarks for Pentium 4: hardware and software issues. ICME (2) (2002)
Franck Cappello, Olivier Richard, Daniel Etiemble
Understanding performance of SMP clusters running MPI programs. Future Gener. Comput. Syst. 17 (6) (2001)
Franck Cappello, Daniel Etiemble
MPI versus MPI+OpenMP on IBM SP for the NAS Benchmarks. SC (2000)
Franck Cappello, Olivier Richard, Daniel Etiemble
Investigating the Performance of Two Programming Models for Clusters of SMP PCs. HPCA (2000)
Franck Cappello, Olivier Richard, Daniel Etiemble
Performance of the NAS Benchmarks on a Cluster of SMP PCs Using a Parallelization of the MPI Programs with OpenMP. PaCT (1999)
Franck Cappello, Olivier Richard, Daniel Etiemble
Performance Evaluation of Two Programming Models for a Cluster of PC Biprocessors. PDPTA (1999)
P. Bosch, A. Carloganu, Daniel Etiemble
Complete x86 instruction trace generation from hardware bus collect. EUROMICRO (1997)
Franck Cappello, Daniel Etiemble
Communications in Parallel Architectures and Networks of Workstations: From Standardisation to New Standards. PaCT (1997)
A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble
Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. EUROMICRO (1997)
Cécile Germain, Jacques Laminie, M. Pallud, Daniel Etiemble
An HPF Case Study of a Domain-Decomposition Based Irregular Application. PaCT (1997)
Keivan Navi, Daniel Etiemble
From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. ISMVL (1995)
Daniel Etiemble, Cécile Germain
Standard Microprocessors Versus Custom Processing Elements for Massively Parallel Architectures. PaCT (1995)
Keivan Navi, A. Kazeminejad, Daniel Etiemble
Performance of CMOS Current Mode Full Adders. ISMVL (1994)
A. Kazeminejad, Keivan Navi, Daniel Etiemble
CML Current Mode Full Adders for 2.5-V Power Supply. ISMVL (1994)
Daniel Etiemble, Jean-Claude Syre
Parallel architecture and language in Europe. Future Gener. Comput. Syst. 10 (1) (1994)
Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble
Hardware features of the static communication network of a parallel architecture. Microprocess. Microprogramming 38 (1-5) (1993)
Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Damien Gautier de Lahaut, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
A Parralel Architecture Based on Compiled Communication Schemes. PARCO (1993)
Cécile Germain, Jean-Luc Béchennec, Daniel Etiemble, Jean-Paul Sansonnet
A Communication Architecture for a Massively Parallel Message-Passing Multicomputer. J. Parallel Distributed Comput. 19 (4) (1993)
Daniel Etiemble, Keivan Navi
A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems. ISMVL (1993)
Daniel Etiemble, Keivan Navi
Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system. IEEE Symposium on Computer Arithmetic (1993)
Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
Balanced Distributed Memory Parallel Computers. ICPP (1) (1993)
Daniel Etiemble
On the Performance of Multivalued Integrated Circuits: Past, Present and Future. ISMVL (1992)
Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble
3D hardware packages for parallel architectures. Microprocessing and Microprogramming 32 (1-5) (1991)
Daniel Etiemble, Christophe Chanussot, Vincent Néri
4-Valued BiCMOS Circuits for the Transmission System of a Massively Parallel Architecture. ISMVL (1990)
Franck Cappello, Jean-Luc Béchennec, Daniel Etiemble
A risc central processing unit for a massivelly parallel architecture. Microprocessing and Microprogramming 30 (1-5) (1990)
Daniel Etiemble, Michel Israël
Comparison of Binary and Multivalued ICs According to VLSI Criteria. Computer 21 (4) (1988)
Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec
A highly parallel processor with an instruction set including relational algebra. ICCD (1988)
Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec, He Hé
The Database Processor 'RAPID'. IWDM (1987)
Daniel Etiemble, V. Adeline, Nguyen H. Duyet, J. C. Ballegeer
Micro-computer oriented algorithms for delay evaluation of MOS gates. DAC (1984)
Daniel Etiemble
L Circuits for TSC Checkers. IEEE Trans. Computers 29 (6) (1980)
Daniel Etiemble
TTL circuits for a 4-valued bus a way to reduce package and interconnections. MVL (1978)
Daniel Etiemble, Michel Israël
Implementation of Ternary Circuits with Binary Integrated Circuits. IEEE Trans. Computers 26 (12) (1977)