Jean-Luc Béchennec

Publication Activity (10 Years)

Years Active: 1987-2024
Publications (10 Years): 21

Top Topics

Sequence Diagrams

Embedded Software

Formal Verification

Top Venues

ACM Trans. Embed. Comput. Syst.

Discret. Event Dyn. Syst.

Publications

Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems. CGO (2024)
Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, B. Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, A. Sintzoff, J. R. Coulon
Securing a RISC-V architecture: A dynamic approach. DATE (2023)
Imane Haur, Jean-Luc Béchennec, Olivier H. Roux
Formal verification process of the compliance of a multicore AUTOSAR OS. Softw. Qual. J. 31 (2) (2023)
Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Olivier H. Roux
Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. Discret. Event Dyn. Syst. 33 (1) (2023)
Imane Haur, Jean-Luc Béchennec, Olivier H. Roux
Formal Verification of the Inter-core Synchronization of a Multi-core RTOS Kernel. ICFEM (2022)
Imane Haur, Jean-Luc Béchennec, Olivier H. Roux
High-level Colored Time Petri Nets for true concurrency modeling in real-time software. CoDIT (2022)
Jean-Luc Béchennec, Didier Lime, Olivier H. Roux
Logical time control of concurrent DES. Discret. Event Dyn. Syst. 31 (2) (2021)
Vincent Lostanlen, Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Mathieu Lagrange
Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. Audio Mostly Conference (2021)
Imane Haur, Jean-Luc Béchennec, Olivier Henri Roux
Formal schedulability analysis based on multi-core RTOS model. RTNS (2021)
Khaoula Boukir, Jean-Luc Béchennec, Anne-Marie Déplanche
Requirement specification and model-checking of a real-time scheduler implementation. RTNS (2020)
Jean-Luc Béchennec, Didier Lime, Olivier H. Roux
Control of DES with Urgency, Avoidability and Ineluctability. ACSD (2019)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. EDCC (2018)
Khaoula Boukir, Jean-Luc Béchennec, Anne-Marie Déplanche
Formal approach for a verified implementation of Global EDF in Trampoline. RTNS (2018)
Jean-Luc Béchennec, Olivier Henry Roux, Tigori Kabland Toussaint Gautier
Formal model-based conformance verification of an OSEK/VDX compliant RTOS. CoDIT (2018)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday
HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems. AHS (2018)
Jean-Luc Béchennec, Sébastien Faucou, Olivier H. Roux, Matthias Brun, Louis-Marie Givel
Testing Real-Time Systems With Runtime Enforcement. IEEE Des. Test 35 (4) (2018)
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. VECoS (2017)
Tigori Kabland Toussaint Gautier, Jean-Luc Béchennec, Sébastien Faucou, Olivier Henry Roux
Formal Model-Based Synthesis of Application-Specific Static RTOS. ACM Trans. Embed. Comput. Syst. 16 (4) (2017)
Louis-Marie Givel, Jean-Luc Béchennec, Matthias Brun, Sébastien Faucou, Olivier H. Roux
Testing real-time embedded software using runtime enforcement. SIES (2016)
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
BEST: a Binary Executable Slicing Tool. WCET (2016)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
Hardware runtime verification of embedded software in SoPC. SIES (2016)
Tigori Kabland Toussaint Gautier, Jean-Luc Béchennec, Olivier Henry Roux
Formal Synthesis of Optimal RTOS. HPCC/CSS/ICESS (2015)
Sylvain Cotard, Audrey Queudet, Jean-Luc Béchennec, Sébastien Faucou, Yvon Trinquet
STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems. ACM Trans. Embed. Comput. Syst. 14 (4) (2015)
Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet
Improving processor hardware compiled cycle accurate simulation using program abstraction. SimuTools (2014)
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Olivier H. Roux
Reactive embedded device driver synthesis using logical timed models. SIMULTECH (2014)
Franck Cassez, Jean-Luc Béchennec
Timing Analysis of Binary Programs with UPPAAL. ACSD (2013)
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Sebastien Dube, Olivier H. Roux
Device driver synthesis for embedded systems. ETFA (2013)
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. J. Syst. Archit. 58 (8) (2012)
Sylvain Cotard, Sébastien Faucou, Jean-Luc Béchennec, Audrey Queudet, Yvon Trinquet
A Data Flow Monitoring Service Based on Runtime Verification for AUTOSAR. HPCC-ICESS (2012)
Jean-Luc Béchennec, Mikaël Briday, Valere Alibert
Extending Harmless architecture description language for embedded real-time systems validation. SIES (2011)
Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday, Rola Kassem
An Architecture Description Language for Embedded Hardware Platforms. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 44 (2011)
Jean-Luc Béchennec, Franck Cassez
Computation of WCET using Program Slicing and Real-Time Model-Checking CoRR (2011)
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin, Fabien Juif
ViPER: a lightweight approach to the simulation of distributed and embedded software. SimuTools (2010)
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
Instruction set simulator generation using HARMLESS, a new hardware architecture description language. SimuTools (2009)
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
Simulator generation using an automaton based pipeline model for timing analysis. IMCSIT (2008)
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Yvon Trinquet
Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification. ETFA (2006)
Nathalie Drach, Jean-Luc Béchennec, Olivier Temam
Increasing hardware data prefetching performance using the second-level cache. J. Syst. Archit. 48 (4-5) (2002)
Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches. HPCA (2000)
Claude Limousin, Alexis Vartanian, Jean-Luc Béchennec
PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation. Euro-Par (1999)
Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
3D Parallel Rendering Machine with Texture Caches. Euro-Par (1999)
Julien Sébot, Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
A Parallel Algorithm for 3D Geometry Transformations in OpenGL. Euro-Par (1999)
Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
Evaluation of High Performance Multicache Parallel Texture Mapping. International Conference on Supercomputing (1998)
Jean-Luc Béchennec
ASF: a teaching and rsearch object-oriented simulation tool for computer architecture design and performance evaluation. WCAE@ISCA (1998)
A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble
Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. EUROMICRO (1997)
Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble
Hardware features of the static communication network of a parallel architecture. Microprocess. Microprogramming 38 (1-5) (1993)
Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Damien Gautier de Lahaut, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
A Parralel Architecture Based on Compiled Communication Schemes. PARCO (1993)
Cécile Germain, Jean-Luc Béchennec, Daniel Etiemble, Jean-Paul Sansonnet
A Communication Architecture for a Massively Parallel Message-Passing Multicomputer. J. Parallel Distributed Comput. 19 (4) (1993)
E. Daugeras, Jean-Luc Béchennec, Franck Cappello
Static computation of standard linear algebra subroutines for PTAH. PDP (1993)
Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
Balanced Distributed Memory Parallel Computers. ICPP (1) (1993)
Franck Cappello, Jean-Luc Béchennec, J.-L. Glavitto
Design of the processing node of the PTAH 64 parallel computer. Microprocess. Microprogramming 35 (1-5) (1992)
Franck Cappello, Jean-Luc Béchennec, Jean-Louis Giavitto
PTAH: Introduction to a New Parallel Architecture for Highly Numeric Processing. PARLE (1992)
Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble
3D hardware packages for parallel architectures. Microprocessing and Microprogramming 32 (1-5) (1991)
Franck Cappello, Jean-Luc Béchennec, Daniel Etiemble
A risc central processing unit for a massivelly parallel architecture. Microprocessing and Microprogramming 30 (1-5) (1990)
Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec
A highly parallel processor with an instruction set including relational algebra. ICCD (1988)
Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec, He Hé
The Database Processor 'RAPID'. IWDM (1987)