Mikaël Briday

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 12

Top Topics

Embedded Software

Abstract Interpretation

Timed Petri Nets

Top Venues

Discret. Event Dyn. Syst.

Audio Mostly Conference

Publications

Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems. CGO (2024)
Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, B. Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, A. Sintzoff, J. R. Coulon
Securing a RISC-V architecture: A dynamic approach. DATE (2023)
Rémi Parrot, Mikaël Briday, Olivier H. Roux
Design and verification of pipelined circuits with Timed Petri Nets. Discret. Event Dyn. Syst. 33 (1) (2023)
Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Olivier H. Roux
Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. Discret. Event Dyn. Syst. 33 (1) (2023)
Rémi Parrot, Mikaël Briday, Olivier H. Roux
Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design. Petri Nets (2021)
Rémi Parrot, Mikaël Briday, Olivier H. Roux
Pipeline Optimization using a Cost Extension of Timed Petri Nets. ARITH (2021)
Vincent Lostanlen, Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Mathieu Lagrange
Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. Audio Mostly Conference (2021)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. EDCC (2018)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday
HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems. AHS (2018)
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. VECoS (2017)
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
BEST: a Binary Executable Slicing Tool. WCET (2016)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
Hardware runtime verification of embedded software in SoPC. SIES (2016)
Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet
Improving processor hardware compiled cycle accurate simulation using program abstraction. SimuTools (2014)
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Olivier H. Roux
Reactive embedded device driver synthesis using logical timed models. SIMULTECH (2014)
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Sebastien Dube, Olivier H. Roux
Device driver synthesis for embedded systems. ETFA (2013)
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. J. Syst. Archit. 58 (8) (2012)
Jean-Luc Béchennec, Mikaël Briday, Valere Alibert
Extending Harmless architecture description language for embedded real-time systems validation. SIES (2011)
Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday, Rola Kassem
An Architecture Description Language for Embedded Hardware Platforms. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 44 (2011)
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin, Fabien Juif
ViPER: a lightweight approach to the simulation of distributed and embedded software. SimuTools (2010)
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
Instruction set simulator generation using HARMLESS, a new hardware architecture description language. SimuTools (2009)
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
Simulator generation using an automaton based pipeline model for timing analysis. IMCSIT (2008)
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Yvon Trinquet
Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification. ETFA (2006)