Timing-resilient Network-on-Chip architectures.

Alexandros Panteloukas Anastasios Psarras Chrysostomos Nicopoulos Giorgos Dimitrakopoulos

Published in: IOLTS (2015)

Keyphrases

network on chip
interconnection networks
routing algorithm
network simulator
multi processor
packet switched
data transfer
fault tolerant
data access
parallel algorithm
ad hoc networks
message passing
power dissipation
multi core processors
routing protocol
multistage
energy consumption
wireless sensor networks