A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension.
Karyofyllis PatsidisDimitris KonstantinouChrysostomos NicopoulosGiorgos DimitrakopoulosPublished in: Microprocess. Microsystems (2018)
Keyphrases
- instruction set
- low cost
- embedded systems
- floating point
- application specific
- computer architecture
- field programmable gate array
- processor core
- data structure
- real time
- efficient implementation
- general purpose
- low power consumption
- hardware and software
- quadtree
- cost effective
- database management systems
- memory access