A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS.
Paul N. WhatmoughShidhartha DasDavid M. BullPublished in: ISSCC (2013)
Keyphrases
- low power
- error correction
- high speed
- cmos technology
- power consumption
- nm technology
- low cost
- real time
- single chip
- error detection
- vlsi circuits
- data hiding
- low voltage
- digital signal processing
- error correcting
- power reduction
- vlsi architecture
- mixed signal
- delay insensitive
- power dissipation
- image sensor
- turbo codes
- low power consumption
- filter bank
- low density parity check
- ultra low power
- watermarking scheme
- ldpc codes
- channel coding
- computer simulation