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Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms.
Paul N. Whatmough
Shidhartha Das
David M. Bull
Izzat Darwazeh
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2013)
Keyphrases
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low power
high speed
digital signal processing
error tolerance
logic circuits
power consumption
low cost
cmos technology
gate array
power dissipation
vlsi circuits
delay insensitive
single chip
power reduction
vlsi architecture
low power consumption
image sensor
real time
mixed signal
signal processing
nm technology