Login / Signup

A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.

David M. BullShidhartha DasKarthik ShivashankarGanesh S. DasikaKrisztián FlautnerDavid T. Blaauw
Published in: ISSCC (2010)
Keyphrases
  • error tolerance
  • error detection and correction
  • high speed