A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS.
Paul N. WhatmoughShidhartha DasDavid M. BullPublished in: IEEE J. Solid State Circuits (2014)
Keyphrases
- low power
- error correction
- high speed
- cmos technology
- power consumption
- nm technology
- low cost
- real time
- single chip
- vlsi circuits
- power reduction
- error detection
- data hiding
- digital signal processing
- power dissipation
- error correcting
- image sensor
- channel coding
- low voltage
- vlsi architecture
- low power consumption
- filter bank
- mixed signal
- delay insensitive
- low density parity check
- ultra low power
- watermarking scheme
- turbo codes
- wireless sensor networks