A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist.
Nan-Chun LienLi-Wei ChuChien-Hen ChenHao-I YangMing-Hsien TuPaul-Sen KanYong-Jyun HuChing-Te ChuangShyh-Jye JouWei HwangPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2014)