A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.
Wei-Nan LiaoNan-Chun LienChi-Shin ChangLi-Wei ChuHao-I YangChing-Te ChuangShyh-Jye JouWei HwangMing-Hsien TuHuan-Shun HuangJian-Hao WangPaul-Sen KanYong-Jyun HuPublished in: SoCC (2013)