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A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing.

Ming-Hsien TuJihi-Yu LinMing-Chien TsaiChien-Yu LuYuh-Jiun LinMeng-Hsueh WangHuan-Shun HuangKuen-Di LeeWei-Chiang ShihShyh-Jye JouChing-Te Chuang
Published in: IEEE J. Solid State Circuits (2012)
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