• search
    search
  • reviewers
    reviewers
  • feeds
    feeds
  • assignments
    assignments
  • settings
  • logout

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist.

Yi-Wei ChiuYu-Hao HuMing-Hsien TuJun-Kai ZhaoYuan-Hua ChuShyh-Jye JouChing-Te Chuang
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
Keyphrases