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40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist.

Yi-Wei ChiuYu-Hao HuMing-Hsien TuJun-Kai ZhaoYuan-Hua ChuShyh-Jye JouChing-Te Chuang
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
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