A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.
Chao-Kuei ChungChien-Yu LuZhi-Hao ChangShyh-Jye JouChing-Te ChuangMing-Hsien TuYu-Hsian ChenYong-Jyun HuPaul-Sen KanHuan-Shun HuangKuen-Di LeeYung-Shin KaoPublished in: SoCC (2014)