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SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage.
Saibal Mukhopadhyay
Rahul M. Rao
Jae-Joon Kim
Ching-Te Chuang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
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random access memory
low voltage
steady state
line segments
real time
significant improvement
key features
positive and negative
data sets
decision trees
low power