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A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.

Rajiv V. JoshiRouwaida KanjKeunwoo KimRichard Q. WilliamsChing-Te Chuang
Published in: ISLPED (2007)
Keyphrases
  • low voltage
  • random access memory
  • design considerations
  • cmos technology
  • power line
  • power management
  • leakage current
  • power consumption
  • low power
  • real time