Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices.
Yin-Nien ChenMing-Long FanVita Pi-Ho HuPin SuChing-Te ChuangPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
Keyphrases
- low power
- high speed
- low power consumption
- logic circuits
- wireless transmission
- vlsi circuits
- real time
- power consumption
- single chip
- cmos technology
- power reduction
- energy dissipation
- power dissipation
- high power
- low cost
- mixed signal
- digital signal processing
- frame rate
- vlsi architecture
- delay insensitive
- chip design
- gate array
- focal plane
- channel capacity
- multi channel
- associative memory
- ultra low power