Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.
Rajiv V. JoshiSaibal MukhopadhyayDonald W. PlassYuen H. ChanChing-Te ChuangYue TanPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- low power
- cmos technology
- power consumption
- low power consumption
- single chip
- low cost
- high speed
- power reduction
- nm technology
- logic circuits
- vlsi architecture
- power dissipation
- digital signal processing
- silicon on insulator
- gate array
- mixed signal
- high power
- vlsi circuits
- wireless transmission
- ultra low power
- signal processor
- delay insensitive
- design methodology
- design process