Thomas J. Bucelot

Publication Activity (10 Years)

Years Active: 2002-2015
Publications (10 Years): 0

Top Topics

Clock Frequency

Top Venues

Publications

David Shan, Phillip J. Restle, Doug Malone, Robert A. Groves, Eric Lai, Michael Koch, Jason Hibbeler, Yong Kim, Christos Vezyrtzis, Jan Feder, David Hogenmiller, Thomas J. Bucelot
. VLSIC (2015)
Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich
microprocessor. ISSCC (2014)
Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot
On-chip circuit for measuring multi-GHz clock signal waveforms. VTS (2013)
Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. IEEE J. Solid State Circuits 44 (1) (2009)
Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor. ISSCC (2008)
Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI (2005)
Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. IEEE J. Solid State Circuits 38 (3) (2003)
Gregory P. Rodgers, Isidore G. Bendrihem, Thomas J. Bucelot, Barry D. Burchett, John C. Collins
Infrastructure requirements for a large-scale, multi-site VLSI development project. IBM J. Res. Dev. 46 (1) (2002)
Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. CICC (2002)