Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.
Gerald G. LopezGiovanni FiorenzaThomas J. BucelotPhillip J. RestleMary Yvonne LanzerottiPublished in: ACM Great Lakes Symposium on VLSI (2005)
Keyphrases
- high speed
- design process
- engineering design
- user interface
- real time
- information technology
- probability distribution
- user experience
- uniformly distributed
- global information
- spatial distribution
- design decisions
- conceptual model
- computer aided
- software development
- wireless sensor networks
- control system
- data mining