A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors.
Hitoshi OkamuraHideo ToyoshimaKoichi TakedaTakashi OguriSatoshi NakamuraMasahide TakadaKiyotaka ImaiYasushi KinoshitaHiroshi YoshidaTom YamazakiPublished in: IEEE J. Solid State Circuits (1995)
Keyphrases
- power consumption
- random access memory
- low power
- cmos technology
- power dissipation
- random access
- memory access
- circuit design
- low voltage
- low cost
- knowledge base
- embedded dram
- secondary storage
- chip design
- nm technology
- power management
- high speed
- read write
- memory usage
- design considerations
- ad hoc networks
- flash memory
- data center
- single chip
- access control
- delay insensitive
- image sensor
- memory space
- high density
- routing protocol
- data structure